The present application relates generally to semiconductor device processing. More particularly, the present invention relates to eliminating systematic process yield loss via precision wafer placement alignment when processing semiconductor devices.
Processes to define electronic devices and interconnect on and near the surface of semiconductor substrates or wafers are well known. Such processes including patterning the surface using photoresist, etching materials by photolithography, ion implantation to define devices and film deposition and patterning for interconnect. These processes are generally well understood and are under constant refinement to improve yield. Yield is the percentage of good semiconductor chips produced from a substrate. These and other processes are also under refinement to allow definition of ever smaller geometries.
Two methods for achieving smaller geometries are by defining more vertically oriented devices, and by improving the electrical isolation between devices. This can be done by etching deep trenches in the surface of the semiconductor substrate. In subsequent process steps, the trenches can be filled with different materials to achieve desirable effects. For example, a trench filled with an insulator such as silicon dioxide will electrically isolate adjacent silicon islands, reducing the electrical interaction of devices built therein. As another example, a trench filled with a conducting layer such as polysilicon which is separated in the trench with a thin insulating oxide can form a charge storage capacitor for a dynamic random access memory.
One conventional method of forming deep trenches on semiconductor surfaces is by plasma etching. Plasma etching occurs in an evacuated chamber in which a wafer is placed on an electrostatic chuck (ESC) which forms the cathode of a parallel plate plasma reactor. The ESC is cooled internally, by liquid cooling systems, to manage the temperature of the wafer. Heat is carried away from the back side of the wafer while the front side is being etched. A gas plasma is introduced to the chamber to provide ions or free radicals for the etching process. Radio frequency energy is applied to drive the plasma and the etching process. A focus ring may be added to focus or concentrate the reactive ions or free radicals. A computer based controller controls the operation according to a program of instructions which reflects the required times, temperatures and other processing conditions required for etching particular films. The process may be even further automated by adding a robot which places wafers in the chamber from a previous process or storage location and removes the wafers after etching for a subsequent process step. A well designed etching process will commonly produce very high yields across the entire wafer surface.
In semiconductor processes, while reduction in yield loss is always one goal of process improvement, small levels of yield loss have been tolerated as normal. A large yield loss is not tolerated and processing equipment will be taken off line while a yield problem is isolated and corrected. In the case of intermediate yield losses, attempts at resolution are made by various unscheduled maintenance procedures. For example, in a plasma etching process, adjustments to back side cooling pressures or process gases can temporarily improve the problem. These adjustments, however, may be masking the true source of the problem and are not a long term solution to eliminate yield loss.
Accordingly, there is a need for an improved method for reducing process yield loss in semiconductor processing.